MSE Master of Science in Engineering

The Swiss engineering master's degree

Each module contains 3 ECTS. You choose a total of 10 modules/30 ECTS in the following module categories: 

  • 12-15 ECTS in technical scientific modules (TSM)
    TSM modules teach profile-specific specialist skills and supplement the decentralised specialisation modules.
  • 9-12 ECTS in fundamental theoretical principles modules (FTP)
    FTP modules deal with theoretical fundamentals such as higher mathematics, physics, information theory, chemistry, etc. They will teach more detailed, abstract scientific knowledge and help you to bridge the gap between abstraction and application that is so important for innovation.
  • 6-9 ECTS in context modules (CM)
    CM modules will impart additional skills in areas such as technology management, business administration, communication, project management, patent law, contract law, etc.

In the module description (download pdf) you find the entire language information per module divided into the following categories:

  • instruction
  • documentation
  • examination 
Design of Embedded Hardware and Firmware (TSM_EmbHardw)

This module introduces the student to advanced concepts in modern embedded systems engineering. The module is divided into two sections. The first section is practical/theoretical and is designed to get the student familiar with implementing System on Chip (SoC) designs. The second part discusses formal Hardware/Software Co-Design including design and implementation of advanced embedded architectures as well as the verification and test of the resulting system.  


The students have a working knowledge of programming embedded systems in C.
The students have a working knowledge of basic hardware design including VHDL coding

Learning Objectives

  • The student will know some of the forces driving the design of modern embedded architectures.
  • The student will understand and be able to apply the V-Model and structured HW/SW Co-Design methodologies including strategies for the verification and test of embedded systems.  
  • The student will be able to design and implement complete SoC designs including using soft-core microprocessors and IP cores in an FPGA.
  • The student will be able to apply loop optimisations using both SW techniques and optimised cache in single- and multi-processor architectures.
  • The students will be able to understand and apply pipeline architectures in processors (super-pipelined, superscalar), HW and SW.


Contents of Module

  • Introduction
    • V-Model, specification and test
    • HW-SW Co-Design
  • SoC design, implementation and test
    • FPGA technology, SoC design, soft-core processors, design, implementation and reuse of custom IP cores
    • Bus systems
  • Optimisation Strategies
    • Advanced peripherals, DMA, scheduling
    • Software loop optimisations, custom instructions, co-processors,
    • Memory hierarchy (cache, scratch pad memories ) 
    • Pipeline, multiprocessing
  • Review
    • Exercises and laboratories using an FPGA board

Teaching and Learning Methods

Accompanied exercises


No mandatory literature

Download full module description